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data bulletin CMX654 1998 mx-com, inc. www. mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480186.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. v.23 transmit modulator preliminary information features applications x 1200bits/sec, v.23 transmit modulator x 3.0v to 5.5v supply: 1ma typical at 3v x zero power mode: 1a typical x 1200bits/sec tx data retiming x 3.58mhz xtal/clock rate x meets itu and etsi specifications x caller id generation for: isdn terminal adapters wireless local loop system isdn pabx applications pair-gain systems public switched telephone networks trunk exchanges digital line circuit codec c v23 transmit modulator slic dtmf decoder ringing generator dc-to-dc converter pots CMX654 the CMX654 is a low power integrated circuit, designed for the transmission of asynchronous 1200bits/sec data in accordance with itu, v.23 and etsi specifications. the device incorporates an optional tx data retiming function. this device may be operated so that only the mark or space tone is produced. the CMX654 may be used in a wide range of telephone telemetry systems. with a low voltage requirement of 3.0v it is suitable for both portable terminal and line powered applications. a very low current 'sleep' mode (1 p a typ.) and an operating current of 1ma typ. makes the CMX654 ideal for line powered applications. this device requires a standard 3.58mhz xtal/clock rate and operates from a 3.0 to 5.5v supply. available packages are: 16-pin soic (CMX654d4) and 16-pin pdip (CMX654p3). additional package styles may be available to meet specific design requirements.
v.23 transmit modulator 2 CMX654 preliminary information 1998 mx-com, inc. www. mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480186.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. contents section page 1 block diagram................................................................................................................ 3 2 signal list................................................................................................................... .... 4 3 external components.................................................................................................... 5 4 general description....................................................................................................... 6 4.1 xtal oscillator and clock dividers ....................................................................................... 6 4.2 mode control logic .......................................................................................................... ... 6 4.3 fsk modulator and transmit filter...................................................................................... 6 4.4 tx data retiming............................................................................................................ ..... 7 5 application notes .......................................................................................................... 8 5.1 line interface.............................................................................................................. ......... 8 6 performance specification............................................................................................ 9 6.1 electrical performance ...................................................................................................... .. 9 6.1.1 absolute maximum ratings.................................................................................................. .. 9 6.1.2 operating limits .......................................................................................................... ........... 9 6.1.3 operating characteristics................................................................................................. .... 10 6.2 timing...................................................................................................................... .......... 11 6.3 packaging................................................................................................................... ....... 12 mx-com, inc reserves the right to change specification at any time and without notice.
v.23 transmit modulator 3 CMX654 preliminary information 1998 mx-com, inc. www. mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480186.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 1 block diagram txd m0 clk rdy m1 mode control logic tx data re-timing transmit filter and output buffer fsk modulator txout xtal osc and clock dividers xtal/ clock xtal v dd v bias v s s CMX654 figure 1: block diagram
v.23 transmit modulator 4 CMX654 preliminary information 1998 mx-com, inc. www. mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480186.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 2 signal list d4/p3 signal description pin no. name type 1 xtal input the output of the on-chip xtal oscillator inverter. 2 xtal/clock input the input to the on-chip xtal oscillator inverter. 3 m0 input a logic level input for setting the mode of the device. see section 4.2. 4 m1 input a logic level input for setting the mode of the device. see section 4.2. 5 connect to v ss . 6 n/c no connection, do not connect to this pin. 7 txout output the output of the fsk generator. 8v ss power the negative supply rail (ground). 9v bias output internally generated bias voltage, held at v dd /2 when the device is not in 'zero-power' mode. should be decoupled to v ss by a capacitor mounted close to the device pins. 10 - - connect to v dd . 11 txd input a logic level input for either the raw input to the fsk modulator or data to be re-timed depending on the state of the m0, m1 and clk inputs. see section 4.3. 12 clk input a logic level input which may be used to clock data bits into the tx fsk data retiming block. 13 - n/c no connection, do not connect to this pin. 14 - n/c no connection, do not connect to this pin. 15 rdy output "ready for tx data transfer" output of the on-chip data retiming circuit. this open-drain active low output may be used as an interrupt request/wake-up input to the associated p c. an external pull-up resistor should be connected between this output and v dd . 16 v dd power the positive supply rail. levels and thresholds within the device are proportional to this voltage. should be decoupled to v ss by a capacitor mounted close to the device pins. v dd and v bias decouplin g is very important. it is recommended that the decouplin g capacitors be placed so that connections between them and the device pins are as short as practicable. table 1: signal list
v.23 transmit modulator 5 CMX654 preliminary information 1998 mx-com, inc. www. mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480186.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 3 external components v dd v dd v bias v ss CMX654 d4/p3 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 n/c n/c n/c rdy clk txd m1 txout m0 to / fr o m c from c c1 c2 c3 c4 x1 r1 xtal/clock xtal figure 2: external components r1 100k : c1, c2 18pf c3 0.1 p f c4 0.1 p f x1 note 1 3.579545mhz resistors r 5%, capacitors r 10% unless otherwise stated table 2: external components for typical application external components notes: 1. a crystal frequency of 3.579545mhz r 0.1% is required for correct fsk operation. for best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of v dd , peak-peak. tuning fork crystals generally cannot meet this requirement. to obtain crystal oscillator design assistance, consult your crystal manufacturer. operation of this device without a xtal or clock input may cause device damage.
v.23 transmit modulator 6 CMX654 preliminary information 1998 mx-com, inc. www. mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480186.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 4 general description 4.1 xtal oscillator and clock dividers frequency and timing accuracy of the CMX654 is determined by a 3.579545mhz clock present at the xtal/clock pin. this may be generated by the on-chip oscillator inverter using the external components c1, c2 and x1 of figure 2, or may be supplied from an external source to the xtal/clock input. if supplied from an external source, c1, c2 and x1 should not be fitted. the on-chip oscillator is turned off in the 'zero-power' mode. if the clock is provided by an external source, which is not always running, then the 'zero-power' mode must be set when the clock is not available. failure to observe this rule may cause a significant rise in the supply current drawn by CMX654 as well as generating undefined states of the rdy output. 4.2 mode control logic the CMX654's operating mode is determined by the logic levels applied to the m0 and m1 input pins: m1 m0 tx mode data retime [1] 0 1 1200bits/sec tx 10 off - 1 1 'zero-power' - [1] if enabled in the 'zero-power' mode, power is removed from all internal circuitry. when leaving 'zero-power' mode there must be a delay of 20ms before any tx data is passed to the device to allow the bias level, filters and oscillator to stabilize. on applying power to the device the mode must be set to 'zp', i.e. m0=1, m1=1, until v dd has stabilized. 4.3 fsk modulator and transmit filter these blocks produce a tone according to the txd, m0 and m1 inputs as shown in the table below, assuming data retiming is not being used: m1 m0 txd = '0' txd = '1' 1 1 zero power zero power 10 0hz 0hz [1] 0 1 2100hz 1300hz [1] txout held at approx. v dd /2. when modulated at the appropriate baud rates, the transmit filter and associated external components (see section 5.1) limit the fsk out of band energy sent to the line in accordance with figure 3 assuming that the signal on the line is at -6dbm or less.
v.23 transmit modulator 7 CMX654 preliminary information 1998 mx-com, inc. www. mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480186.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. figure 3: tx limits 4.4 tx data retiming the data retiming block, when enabled in 1200bits/sec transmit mode, requires the controlling p c to load 1 bit at a time into the device by a pulse applied to the clk input. the timing of this pulse is not critical and it may easily be generated by a simple software loop. this facility removes the need for a uart in the p c without incurring an excessive software overhead. the tx re-timing circuit consists of two 1-bit registers in series, the input of the first is connected to the txd pin and the output of the second feeds the fsk modulator. the second register is clocked by an internally generated 1200hz signal and when this occurs the clk input is sampled. if the clk input is high the txd pin directly controls the fsk modulator, if the clk input is low the fsk modulator is controlled by the output of the second register and the rdy pin is pulled low. the rdy output is reset by a high level on the clk input pin. a low to high change on the clk input pin will latch the data from the txd input pin into the first register ready for transfer to the second register when the internal 1200hz signal next occurs. so to use the retiming option the clk input should be held low until the rdy output is pulled low. when the rdy pin goes low the next data bit should be applied at the txd input and the clk input pulled high and then low within the time limits set out in figure 7. to ensure synchronization between the controlling device and the CMX654 when entering tx retiming mode, the txd pin must be held at a constant logic level from when the clk pin is first pulled low to the end of loading in the second retimed bit. similarly when exiting tx retiming mode the txd pin should be held at the same logic level as the last retimed bit for at least 2 bit times after the clk line is pulled high. if the data retiming facility is not required, the clk input to the CMX654 should be kept high at all times. the asynchronous data to the fsk modulator will then be connected directly to the txd input pin. this is illustrated in figure 4. n-2 n-2 n-1 n-1 n n n+1 n+1 n+2 n+2 fsk modulator input: txd input: figure 4: fsk operation without tx data retiming (clk always high)
v.23 transmit modulator 8 CMX654 preliminary information 1998 mx-com, inc. www. mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480186.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 5 application notes 5.1 line interface the signals on the telephone line are not suitable for direct connection to the CMX654. a line interface circuit is necessary to: x provide high voltage and dc isolation x provide the low impedance drive necessary for the line x filter the tx and rx signals line 1:1 r3 r6 z txout possible receive - hybrid circuitry v bias a b c a1 0v c5 c7 + figure 5: line interface circuit r3 note 3 c5 22 p f ( r 20%) r6 100k : c7 330pf resistors r 1%, capacitors r 10% unless otherwise stated. notes: 1. the component(s) 'z' between points b and c should match the line impedance. 2. device a1 must be able to drive 'z' and the line. 3. r3: the levels in db (relative to a 775mv rms signal) at 'a', 'b' and 'c' in the line interface circuit are: a' = 20log(v dd /5) 'b' = 'a' + 20log(100k : /r3) 'c' = 'b' - 6 v dd 'a' r3 'b' 'c' 3.3v -3.6db 100k : -3.6db -9.6db 5.0v 0db 150k : -3.5db -9.5db
v.23 transmit modulator 9 CMX654 preliminary information 1998 mx-com, inc. www. mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480186.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 6 performance specification 6.1 electrical performance 6.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. units supply (v dd - v ss ) -0.3 7.0 v voltage on any pin to v ss -0.3 v dd + 0.3 v current into or out of: v dd -30 30 ma v ss -30 30 ma any other pin -20 20 ma d4 / p3 package total allowable power dissipation at t amb = 25c 800 mw derating above 25c 13 mw/c above 25c storage temperature -55 125 c operating temperature -40 85 c 6.1.2 operating limits correct operation of the device outside these limits is not implied. notes min. max. units supply (v dd - v ss )3.05.5v operating temperature -40 85 c xtal frequency 1 3.575965 3.583125 mhz notes: 1. a xtal frequency of 3.579545mhz 0.1% is required for correct fsk operation.
v.23 transmit modulator 10 CMX654 preliminary information 1998 mx-com, inc. www. mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480186.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 6.1.3 operating characteristics for the following conditions unless otherwise specified: v dd = 3.0v at t amb = 25c and v dd = 3.3v to 5.5v at t amb = -40 to +85c, xtal frequency = 3.579545mhz r 0.1%, 0dbv corresponds to 1.0v rms , 0dbm corresponds to 775mv rms into 600 : . notes min. typ. max. units dc parameters i dd (m0='1', m1='1') 1, 2 1 p a i dd (m0 or m1='0') at v dd = 3.0v 1 1.0 1.25 ma i dd (m0 or m1='0') at v dd = 5.0v 1 1.7 2.5 ma logic '1' input level 70% v dd logic '0' input level 30% v dd logic input leakage current (v in = 0 to v dd ), excluding xtal/clock input -1.0 1.0 p a output logic '1' level (l oh = 360 p a) v dd -0.4 v output logic '0' level (l ol = -360 p a) 0.4 v rdy output 'off' state current (v out = v dd ) 1.0 p a fsk retiming tx data rate 1194 1206 baud fsk modulator txout level 3 -1.0 0 1.0 db twist (mark level wrt space level) -2.0 0 2.0 db tx 1200bits/sec (m1='0', m0='1'). bit rate 0 1200 1212 baud mark (logical 1) frequency 1297 1303 hz space (logical 0) frequency 2097 2103 hz xtal/clock input 'high' pulse width 4 100 ns 'low' pulse width 4 100 ns operating characteristics notes: 1. at 25 q c, not including any current drawn from the CMX654 pins by external circuitry other than x1, c1 and c2. 2. txd and clk inputs at v ss , m0 and m1 inputs at v dd . 3. relative to 775mv rms at v dd = 5.0v for load resistance greater than 40k : . 4. timing for an external input to the xtal/clock pin.
v.23 transmit modulator 11 CMX654 preliminary information 1998 mx-com, inc. www. mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480186.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 6.2 timing data and mode timing min. typ. max. units delay to reliable data at txout after zp to tx mode change 20.0 ms data retiming disabled (reference figure 6) tx data delay (txd to txout) 0.1 ms data retiming enabled (reference figure 7) t d = internal CMX654 delay 1 p s tc hi = clk high time 1 p s t r = rdy low to clk going low 800 p s t s = data set-up time 1 p s t h = data hold time 1 p s txd txout (fsk signal) tx data delay f hi f lo f lo f hi note : m0 and m1 are preset and stable. f lo and f hi are the two fsk signaling frequencies. figure 6: txd to txout delay time 1 1 1 2 3 4 3 2 fsk modulator input rdy clk txd t s t h t d t r tc hi rdy clk txd figure 7: fsk operation with tx data retiming
v.23 transmit modulator 12 CMX654 preliminary information 1998 mx-com, inc. www. mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480186.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 6.3 packaging pin 1 a b alternative pin location marking x p j y c k h e l t w z note : all dimensions in inches (mm.) angles are in degrees package tolerances a b c e h typ. max. min. dim. j p x w t y k l 0.105 (2.67) 0.093 (2.36) 0.419 (10.64) 45 7 0 10 0.050 (1.27) 0.041 (1.04) 0.413 (10.49) 0.299 (7.59) 0.050 (1.27) 0.016 (0.41) 0.390 (9.90) 0.020 (0.51) 0.003 (0.08) 0.009 (0.23) 0.0125 (0.32) 0.013 (0.33) 0.020 (0.51) 0.395 (10.03) 0.286 (7.26) z 5 5 figure 8: 16-pin soic (d4) mechanical outline: order as part no. CMX654d4 package tolerances note : all dimensions in inches (mm.) angles are in degrees typ. max. min. a b c e e1 h dim. j j1 p y t k l 0.200 (5.06) 0.262 (6.63) 0.390 (9.91). 7 0.150 (3.81) 0.810 (20.57) 0.135 (3.43) 0.100 (2.54) 0.121 (3.07) 0.300 (7.62) 0.290 (7.37) 0.325 (8.26) 0.015 (0.38) 0.070 (1.77) 0.008 (0.20) 0.015 (0.38) 0.014 (0.35) 0.023 (0.58) 0.040 (1.02) 0.065 (1.65) 0.056 (1.42) 0.064 (1.63) 0.740 (18.80) 0.240 (6.10) b a pin 1 e y e1 t k h j1 j c p l figure 9: 16-pin pdip (p3) mechanical outline: order as part no. CMX654p3

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